1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a bipolar junction transistor (BJT), a complementary MOS (CMOS) transistor and a double diffused MOS (DMOS) transistor, and to a manufacturing method thereof.
2. Description of the Related Art
In a typical complex system for complexly performing signal processing, operations, logic and other functions, each of the functions is performed by semiconductor devices manufactured by various manufacturing processes. For instance, bipolar junction transistors (BJTs) having high transfer conductance, are usually used for an analog circuits. However, complementary MOS (CMOS) transistors having high integration and low frequency are usually used for logic or memory circuits. In particular, double diffused MOS (DMOS) transistors are usually used for circuits requiring operation at high voltages and at high switching speeds.
However, there have been disclosed various processes for manufacturing integrated circuit chips in which both CMOS devices and bipolar devices are formed, and various processes for manufacturing integrated circuit chips in which DMOS devices appropriate for operation at high voltages are formed. Here, the integration of the device is increased; however, the manufacturing process is complex due to the multiple mask layers required for the manufacturing process, and there are limits on the performance of each of the devices. A DMOS device will be described with reference to the attached drawings.
FIG. 1 is a schematic sectional view of a conventional lateral DMOS transistor, and FIG. 2 is an enlarged view of portion A of FIG. 1.
Referring to FIGS. 1 and 2, an n-type well region 2 is formed in a p-type semiconductor substrate 1 such that the well region 2 is adjacent to a surface of the semiconductor substrate 1. A p-type top region 3 having a predetermined length and an n-type drain region 4 are formed in the well region 2. The length of the p-type top region 3 is determined by the voltage Vds between a drain and a source, and is spaced apart from the drain region 4. A p-type body region 5 is formed in another predetermined region of the semiconductor substrate 1, spaced apart from the well region 2 by a predetermined distance. An n-type heavily doped source region 6 and a p-type heavily doped source region 7, which are adjacent to each other, are formed in the p-type body region 5.
A source electrode 8 is formed to be electrically connected to the source region 6, and a drain electrode 9 is formed to be electrically connected to the drain region 4. Also, a gate electrode 10 is formed to be electrically insulated from the semiconductor substrate 1 by a gate insulating layer 11. The source electrode 8, the drain electrode 9 and the gate electrode 10, are electrically insulated by an interdielectric layer.
The above lateral DMOS transistor is turned on or off according to a signal applied to the gate electrode 10 in the state in which a high voltage is applied to the drain electrode 9. Particularly, when the lateral DMOS transistor is used as a power switching device at a high voltage, e.g., 600xcx9c800V and the device is in the on-state, electrons move to the drain region 4 from the source region 6, and energy is stored in an inductor connected to an external circuit. When the device is in the off-state, charges stored in the inductor are discharged, and the discharged current flows to the source electrode 8 through a resistance Rb (of FIG. 2) in the body region 5. When the voltage is dropped by the resistance Rb, and the junction of the body region 5 and the source region 6 is forward-biased by the voltage drop, a parasitic npn BJT 20 (of FIG. 2) formed by the n-type well region 2, the p-type body region 5 and the n-type source region 6 operates. When the parasitic npn BJT 20 operates, the device cannot be controlled by the gate electrode 10 any more, and further, the device may be broken.
There have been proposed various methods for suppressing turn-on of the parasitic npn BJT 20, where a method for reducing the size of resistance Rb in the body region 5 has been studied.
Meanwhile, the breakdown voltage must be increased to use the lateral DMOS transistor at a high voltage. A depletion layer must be extended in the direction of the semiconductor substrate 1 in the well region 2 to realize a high breakdown voltage of 600V or more, and thus a lightly doped p-type semiconductor substrate must be used such that the resistivity becomes approximately 100 xcexa9cm. However, if an NMOS transistor is formed on the lightly doped semiconductor substrate, punchthrough easily occurs in a channel having a length of approximately 3 xcexcm or less, to thereby reduce the breakdown voltage between the drain and the source. Also, if the npn BJT is formed on the semiconductor substrate, an intrinsic base region of the npn BJT is formed with a concentration the same as that of the body region of the DMOS transistor, to thereby deteriorate characteristics of the npn BJT and DC current gain hFE due to the lightly doped base region.
It is an objective of the present invention to provide a semiconductor device having a substrate in which a BJT, a CMOS transistor and a DMOS transistor are formed.
It is another objective of the present invention to provide a method for manufacturing the semiconductor device.
Accordingly, to achieve the first objective, a semiconductor device according to an embodiment of the present invention includes a bipolar junction transistor and a DMOS transistor formed on a semiconductor substrate of a first conductivity type. The DMOS transistor comprises a body region of the first conductivity type and a well region of a second conductivity type formed in a predetermined upper region of the semiconductor substrate, wherein the body region and the well region are spaced by a predetermined interval, a highly-doped bottom layer of the first conductivity type to contact the lower surface of the body region in the semiconductor substrate, a highly-doped source region of the second conductivity type formed in a predetermined upper region of the body region, a highly-doped drain region of a second conductivity type formed in a predetermined upper region of the well region, a gate electrode formed on a channel formation region of the body region wherein an insulating layer is interposed between the gate electrode and the body region, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region.
Here, preferably, the semiconductor device further comprises a top region of the first conductivity type formed in an upper portion of the well region.
Preferably, the bipolar junction transistor comprises a well region of the first conductivity type formed in a predetermined upper portion of the semiconductor substrate, a highly-doped bottom layer of the first conductivity type formed in a predetermined region of the well region, a first base region of the first conductivity type contacting the upper surface of the bottom layer in the well region, a highly-doped second base region of the first conductivity type contacting the upper portion of the bottom layer in the first base region, a highly-doped emitter region of the second conductivity type formed in a part of the surface of the first base region, and a base electrode, an emitter electrode and a collector electrode electrically connected to the second base region, the emitter region and the collector region, respectively;
To achieve the first object, a semiconductor device according to another embodiment of the present invention includes a MOS transistor and a DMOS transistor formed on a substrate of a first conductivity type. Here, the DMOS transistor comprises a body region of the first conductivity type and a well region of a second conductivity type formed in a predetermined upper region of the semiconductor substrate, spaced by a predetermined interval, a highly-doped bottom layer of the first conductivity type to contact a lower surface of the body region in the semiconductor substrate, a highly-doped source region of the second conductivity type formed in a predetermined upper region of the body region, a highly-doped drain region of the second conductivity type formed in a predetermined upper portion of the well region, a gate electrode formed on a channel formation region of the body region wherein an insulating layer is interposed between the gate electrode and the body region, a source electrode to be electrically connected to the source region, and a drain electrode to be electrically connected to the drain region.
Here, preferably, the MOS transistor comprises a highly-doped bottom layer of a first conductivity type formed in a predetermined upper region of the semiconductor substrate, highly-doped source and drain regions of a second conductivity type contacting the upper portion of the bottom layer and spaced apart by a predetermined interval, a gate electrode insulated to a channel formation region between the source region and the drain region by an insulating layer, and source and drain electrodes electrically connected to the source region and the drain region.
To achieve the second object, a method of manufacturing a semiconductor device according to an embodiment of the present invention produces the semiconductor device having a DMOS transistor formed in a first region of a semiconductor substrate of a first conductivity type and a bipolar junction transistor formed in a second region of the semiconductor substrate. By the method, first and second well regions of the second conductivity type are formed in the selected first region and the second region, respectively. Then, highly-doped first and second bottom layers of the first conductivity type are formed in the selected first region and the selected second well region, respectively. An epitaxial layer of the first conductivity type is formed on the first and the second well regions and the semiconductor substrate where the first and the second bottom layers are formed. A drift region of the second conductivity type is formed, having two portions spaced apart by a predetermined interval, and the drift region contacts the upper surface of the first well region in an epitaxial layer of the first region, and a second well extension region is formed in the epitaxial layer of the second region, contacting the upper surface of the second well region. First and second body regions of the first conductivity type are formed in the epitaxial layer of the first region and selected epitaxial layer of the second region to contact the lower surface of the first body region with the upper surface of the first bottom layer and the lower surface of the second body region with the upper surface of the second bottom layer. A gate oxide layer and a gate electrode are sequentially formed on the first region. Highly-doped source and drain regions are formed in the first body region and the selected drift region, a highly-doped base region of the second conductivity type and an emitter region of the first conductivity type in the selected second body region, and a highly-doped collector region of the second conductivity type in the selected second well extension region. Source and drain electrodes are formed on the first region, wherein the source and drain electrodes are electrically connected to the source and the drain regions, respectively. A base electrode, an emitter electrode and a collector electrode are formed on the second region, wherein the a base electrode, an emitter electrode and a collector electrode are electrically are connected to the base region, the emitter region and the collector region, respectively.
Here, preferably, the step of forming the first and the second bottom layers comprises the steps of forming an oxide layer on the semiconductor substrate, forming a photoresist layer pattern exposing a predetermined region of the oxide layer on the semiconductor substrate, implanting impurity ions of the first conductivity type using the photoresist layer pattern as an ion implantation mask, and drive-in diffusing the impurity ions of the first conductivity type. At this time, the thickness of the first and the second bottom layers is 1xcx9c2 xcexcm, and the thickness of the drift region is thinner than the thickness of the epitaxial layer and is half of the thickness of the epitaxial layer.
Preferably, the step of forming the first and the second body regions comprises the steps of forming an oxide layer on the epitaxial layer, forming a photoresist layer pattern exposing predetermined regions of the first and the second regions, on the oxide layer, implanting impurity ions of the first conductivity type using the photoresist layer pattern as an ion implantation mask, and drive-in diffusing impurity ions of the first conductivity type.
To achieve the second object, in a method for manufacturing semiconductor devices according to another embodiment of the present invention, the semiconductor device includes a DMOS transistor formed in a first region of a semiconductor substrate of a first conductivity type and a MOS transistor formed in a second region of the semiconductor substrate. By the method, a well region of the first conductivity type is formed in the selected first region. Then, highly-doped first and second bottom layers of the first conductivity type are formed in a predetermined upper portion of the first region and in the upper portion of the second region. An epitaxial layer of the first conductivity type is formed on the semiconductor substrate where the well region and the first and the second bottom layers are formed. A drift region of the second conductivity type is formed, having two portions spaced apart by a predetermined interval, and the drift region contacts the upper surface of the well region in an epitaxial layer of the first region, and a body region of the first conductivity type is formed, spaced apart from the drift region by a predetermined interval. A gate oxide layer and a gate electrode are sequentially formed on the first and the second regions. Highly-doped source and drain regions of the second conductivity type of the DMOS transistor are formed in the selected body region and the predetermined drift region, and highly-doped source and drain regions of the second conductivity type of the MOS transistor are formed, and the source and drain regions are spaced apart by a predetermined interval in the predetermined epitaxial layer of the second region. Also, source and drain electrodes electrically connected to the source and drain regions of the DMOS transistor and the MOS transistor respectively are formed.
Here, preferably, the epitaxial layer is formed to have a resistivity substantially similar to that of the semiconductor substrate.
Preferably, a predetermined upper portion of the second bottom layer is extended to the epitaxial layer by predetermined annealing in the step of forming the epitaxial layer.
According to the semiconductor device and the method for manufacturing the same, a heavily doped bottom layer is formed under the source region of the DMOS transistor, to thereby suppress turn-on of a sacrificial bipolar transistor, and the source and drain region of a complementary MOS (CMOS) transistor and a base region of a bipolar junction transistor are formed to contact the heavily doped bottom layer, so that the breakdown voltage of the CMOS transistor and the bipolar junction transistor of the device increase reliability.